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E2U0032-28-82 Semiconductor MSM7581 Semiconductor ITU-T G.721 4ch ADPCM TRANSCODER This version: Aug. 1998 MSM7581 Previous version: Nov. 1996 GENERAL DESCRIPTION The MSM7581 is an ADPCM transcoder which is used by the new digital cordless system. It converts 64 kbps voice PCM serial data to 32 kbps ITU-T G.721 ADPCM serial data, and vice versa. This device is consists of four systems with full-duplex voice data channels and a data-through mode. The MSM7581 provides cost effective solutions for digital cordless office telephone systems which are incorporated into PABXs, and for the public base stations which are connected to the Central Office through digital PSTNs. FEATURES * Conforms to ITU-T G.721 * Built-in Full-duplex Transcoder with Four Data Channels * PCM companding Law: A-law/-law selectable * Serial PCM Data Transmission Speed: 64 kbps to 2048 kbps * Serial ADPCM Data Transmission Speed: 32 kbps to 2048 kbps * Hardware Reset - ITU-T G.721 Optional Reset - for each channel * Power Down Control for each channel * Decoder (ADPCM AE PCM ) Mute Mode and PAD Mode for each channel * ADPCM Data-through Mode * Capable of time slot conversion * Special ADPCM Input Data Code ("0000") Detector for each channel * Master Clock Signal : Not necessary * Power supply voltage/Consumption current : +2.7 V to +5.5 V, 2 mA/channel (max) * Package : 100-pin plastic TQFP (TQFP100-P-1414-0.50-K) (Product name : MSM7581TS-K) 1/18 Semiconductor MSM7581 BLOCK DIAGRAM VDD PAD11 PAD10 SYXP1 BCKP1 SIP1 SOP1 SYRP1 RES1 PAD21 PAD20 SYXP2 BCKP2 SIP2 SOP2 SYRP2 RES2 PAD31 PAD30 SYXP3 BCKP3 SIP3 SOP3 SYRP3 RES3 PAD41 PAD40 SYXP4 BCKP4 SIP4 SOP4 SYRP4 RES4 CODER SP DECODER SP PAD/ MUTE CODER SP DECODER SP PAD/ MUTE CODER SP DECODER SP PAD/ MUTE CODER SP DECODER SP PAD/ MUTE +2.7 V to 5.5 V GND LAW 0V PLL MCK CODER DECODER "0000" DETECT CODER PS DECODER PS PLCKEN THR1 PLCK1 SYXA1 BCKA1 SOA1 SIA1 DET1 SYRA1 PDN1 THR2 PLCK2 SYXA2 BCKA2 CODER PS "0000" DETECT DECODER PS SOA2 SIA2 DET2 SYRA2 PDN2 THR3 PLCK3 SYXA3 BCKA3 CODER PS "0000" DETECT DECODER PS SOA3 SIA3 DET3 SYRA3 PDN3 THR4 PLCK4 SYXA4 BCKA4 CODER PS "0000" DETECT DECODER PS SOA4 SIA4 DET4 SYRA4 PDN4 PLL MCK CODER DECODER PLL MCK CODER DECODER PLL MCK CODER DECODER 2/18 Semiconductor MSM7581 PIN CONFIGURATION (TOP VIEW) PLCKEN SYRP1 SYRP4 BCKP1 SYXP1 SYXP4 BCKP4 PAD10 PAD11 PAD41 PAD40 SOP1 SOP4 RES1 100 NC RES4 77 SIP1 SIP4 GND VDD NC NC NC NC 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 NC THR1 PLCK1 SYXA1 SOA1 SIA1 NC DET1 SYRA1 BCKA1 NC PDN1 NC PDN2 NC BCKA2 SYRA2 DET2 NC SIA2 SOA2 SYXA2 PLCK2 THR2 NC 76 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC THR4 PLCK4 SYXA4 SOA4 SIA4 NC DET4 SYRA4 BCKA4 NC PDN4 NC PDN3 NC BCKA3 SYRA3 DET3 NC SIA3 SOA3 SYXA3 PLCK3 THR3 NC 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 RES3 GND SYRP2 SYRP3 VDD SOP3 SIP2 SOP2 BCKP2 SYXP2 PAD20 PAD21 PAD31 PAD30 SYXP3 BCKP3 SIP3 LAW NC RES2 NC NC NC NC : No connect pin 100-Pin Plastic TQFP NC NC 50 3/18 Semiconductor MSM7581 PIN AND FUNCTIONAL DESCRIPTIONS GND Ground, 0 V. SIP1, SOP1 PCM serial data input (SIP1) and output (SOP1) for Channel 1. SOP1 is an open-drain output, which goes into a high impedance state after a continuous 8-bit serial data output. SIP2, SOP2 PCM serial data input (SIP2) and output (SOP2) for Channel 2. SOP2 is an open-drain output, which goes into a high impedance state after a continuous 8-bit serial data output. SIP3, SOP3 PCM serial data input (SIP3) and output (SOP3) for Channel 3. SOP3 is an open-drain output, which goes into a high impedance state after a continuous 8-bit serial data output. SIP4, SOP4 PCM serial data input (SIP4) and output (SOP4) Channel 4. SOP4 is an open-drain output, which goes into a high impedance state after a continuous 8-bit serial data output. PAD10 - PAD40, PAD11 - PAD41 PAD mode control. The PCM output can be attenuated by 12 dB or 6 dB and set to an out-of-service pattern (idle pattern) by controlling these pins. Set these pins to digital "0" level during normal operation.The control sequences are as follows: PAD11 - PAD41 0 0 1 1 PAD10 - PAD40 0 1 0 1 Normal 6 dB Loss 12 dB Loss Out-of-service Pattern 4/18 Semiconductor THR1, THR2, THR3, THR4 MSM7581 Control pins for the data-through modes. THR (1 - 4) are for Channel (1 - 4), respectively. The data-through mode is selected when digital "1" is applied to THR (1 - 4). In this mode, 8-bit serial input data applied to SIA (1 - 4) (ADPCM data input) is passed to the PCM serial data output pins, SOP (1 - 4), without any data modification. SOP (1 - 4) go to the high impedance state after the output of 8-bit data has been applied to SIA (1 - 4). Conversely 8-bit serial input data applied to SIP (1 - 4) (PCM data input) is passed to ADPCM serial data output pins, SOA (1 - 4), without any data modification. SOA (1 - 4) go to the high impedance state after the output of 8-bit serial data has been applied to SIP (1 - 4). ADPCM and PCM data interfaces have the mutually independent signal input pins for synchronizing signals. The time slots for data input and output can be exchanged between them. Some timing at which data may be deleted or duplicated as described in "Note on Usage" should not be used. SYXP1 - 4, SYRP1 - 4 Synchronous signal input pins to define PCM data input and output timing for Channel 1 (SIP1, SOP1), Channel 2 (SIP2, SOP2), Channnel 3 (SIP3, SOP3), and Channel 4 (SIP4, SOP4). The synchronous signals SYXA1 and SYRAI (Channel 1), SYXA2 and SYRA2 (Channel 2), SYXA3 and SYRA3 (Channel 3), and SYXA4 and SYRA4 (Channel 4), which define ADPCM data input and output timing are provided. PCM and ADPCM data interfaces can be used at a mutually independent timing except some timing. Note: When PCM and ADPCM data interfaces are used at a mutually independent timing, the timing described in "Note on Usage" should not be used. SYXP signals must be input for PAD signal input processing. BCKP1 - 4 Bit clock input. These signals define the PCM data transmission speed at the PCM data input/output terminals. BCKP (1 - 4) are used for Channel (1 - 4). Since BCKA (1 - 4) defines the data rate of the ADPCM data interface, the PCM and ADPCM data can be input or output at different speeds. LAW PCM data companding law selection. Digital "1" and "0" correspond to A-law and -law, respectively. PDN1, PDN2, PDN3, PDN4 Power down mode selection. PDN1 - 4 can be independently set to power down mode. When digital "0" is applied, these pins are in the power-down mode. 5/18 Semiconductor SIA1, SOA1 MSM7581 ADPCM serial data input (SIA1) and output (SOA1) pins for Channel 1. SOA1 is an open-drain pin and enters to the high impedance state after outputting a continuous 4-bit serial data stream. When the data-through mode is selected, SOA1 enters to the high impedance state after outputting an 8-bit serial data stream. SIA2, SOA2 ADPCM serial data input (SIA2) and output (SOA2) pins for Channel 2. These pins function the same as SIA1 and SOA1. SIA3, SOA3 ADPCM serial data input (SIA3) and output (SOA3) pins for Channel 3. These pins function the same as SIA1 and SOA1. SIA4, SOA4 ADPCM serial data input (SIA4) and output (SOA4) pins for Channel 4. These pins function the same as SIA1 and SOA1. SYXA1 - 4 , SYRA1 - 4 SYXA1, SYXA2, SYXA3, and SYXA4 are synchronous signal input pins to define ADPCM data input and output timings for Channel 1 (SIA1, SOA1), Channel 2 (SIA2, SOA2), Channel 3 (SIA3, SOA3), and Channel 4 (SIA4, SOA4), respectively. Therefore, PCM data interfaces can be used at a mutually independent timing except some timing. Since master clocks are generated by the internal PLL using SYXA1 to SYXA4, a synchronous signal should be input to these pins. Note: When PCM and ADPCM data interfaces are used at a mutually independent timing, the timing described in "Note on Usage" should not be used. DET1, DET2, DET3, DET4 Special ADPCM input data pattern detect pins. When detecting a 4-bit continuous "0" pattern at the ADPCM input pins Channel 1 (SIA1), Channel 2 (SIA2), Channel 3 (SIA3), and Channel 4 (SIA4), DET (1 - 4) goes from a digital "0" to a digital "1" state. A digital "1" is output at the rising edge of the clock. The fourth data bit (LSB) is clocked into the register by the bit clock (BCKA 1 - 4) and held there until the rising edge in the next time frame. When detecting the special data pattern in the next time frame, the digital "1" on the pins DET (1 - 4) is remains. 6/18 Semiconductor RES1, RES2, RES3, RES4 Algorithm reset signal input pins for each Channel (1 - 4) . When digital "0" is applied, the entire transcoder goes to the initial state. This reset is defined by ITU-T G.721 and is an optional reset. The reset width (during "L") should be 125 ms or more. BCKA1 - 4 MSM7581 Bit clock input pins used to define the data transmission speed at the ADPCM interface. Using these pins, the ADPCM data interface can be defined at a speed other than the PCM data interface. VDD Power supply. The device must operate between +2.7 V and +5.5 V. PLCKEN Input pin which enables the output of an 8 kHz clock from the PLLs. This pin generates the internal master clocks. The 8 kHz clocks from the internal PLLs synchronized with external signals applied to SYXA 1 - 4 are output to PLCK 1 - 4. Set this pin at digital "0" during normal operation since it is used as the control pin for testing the IC. PLCK1 - 4 Output pins of the 8 kHz clock from PLLs. When PLCKEN = "1", the 8 kHz clock pulses synchronized with external signals are applied to SYXA1 - 4 outputs. When PLCKEN = "0", "0" level is output to these pins. 7/18 Semiconductor MSM7581 ABSOLUTE MAXIMUM RATINGS Parameter Power Supply Voltage Digital Input Voltage Storage Temperature Symbol VDD VDIN TSTG Condition -- -- -- Rating 0 to 7 -0.3 to VDD + 0.3 -55 to +150 Unit V V C RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Voltage Operating Temperature Digital Input High Voltage Digital Input Low Voltage Bit Clock Frequency Synchronous signal Frequency Clock Duty Ratio Digital Input Rise Time Digital Input Fall Time Synchronous signal Timing CODER Synchronous signal Timing DECODER Synchronous signal Width Data Set-up Time Data Hold Time Symbol VDD Ta VIH VIL FBCLKA FBCLKP FSYNC DC tIr tIf tXS tSX tRS tSR tWS tDS tDH RDL Digital Output Load CDL Condition -- -- All digital input pins BCKA1 - 4 BCKP1 - 4 SYXP1 - 4, SYRP1 - 4 SYXA1 - 4, SYRA1 - 4 BCKA1 - 4, BCKP1 - 4 All Digital Input Pins BCKP1 - 4 to SYXP1 - 4 SYXA1 - 4 to BCKA1 - 4 BCKA1 - 4 to SYRA1 - 4 SYRP1 - 4 to BCKP1 - 4 SYXP1 - 4, SYRP1 - 4 SYXA1 - 4, SYRA1 - 4 -- -- SOP1 - 4, SOA1 - 4 (Pull-up Resistor) SOP1 - 4, SOA1 - 4 DET1 - 4, PLCK1 - 4 Min. 2.7 -30 0.45 VDD 0 32 64 -- 30 -- -- 100 100 100 100 1 BCLK 100 100 500 -- Typ. -- +25 -- -- -- -- 8.0 50 -- -- -- -- -- -- -- -- -- -- -- Max. 5.5 +80 VDD 0.16 VDD 2048 2048 -- 70 50 50 -- -- -- -- 100 -- -- -- 100 Unit V C V V kHz kHz kHz % ns ns ns ns ns ns ms ns ns W pF 8/18 Semiconductor MSM7581 ELECTRICAL CHARACTERISTICS DC Characteristics Parameter Power Supply Current Digital Input High Voltage Digital Input Low Voltage Input Leakage Current Digital Output High Voltage Digital Output Low Voltage Output Leakage Current Input Capacitance Symbol IDD1 IDD2 VIH VIL IIH IIL VOH VOL1 VOL2 IOL CIN Condition Power On Mode: 4 Channels (VDD = 2.7 V to 5.5 V, Ta = -30C to +80C) Min. -- Typ. 5 10 -- -- -- -- -- 0.2 0.2 -- 5 Max. 8 50 VDD 0.16 VDD 2.0 0.5 VDD 0.4 0.4 10 -- Unit mA mA V V mA mA V V V mA pF -- Power Down Mode: 4 Channels All Digital Input Pins 0.45 VDD All Digital Input Pins 0.0 VI = VDD VI = 0 V -- -- DET1 - 4, PLCK1 - 4 : IOH = -0.4 mA 0.5 VDD SOA1 - 4, SOP1 - 4, Pull-up 500 W DET1 - 4, PLCK1 - 4 : IOL = 2 mA SOP1 - 4, SOA1 - 4 All Digital Input Pins 0.0 0.0 -- -- AC Characteristics Parameter Symbol tSDX tSDR tXD1, tRD1 Digital Output Delay Time tXD2, tRD2 tXD3, tRD3 tDD1 tDD2 1 LSTTL + 100 pF Pull-up: 500 W Condition (VDD = 2.7 V to 5.5 V, Ta = -30C to +80C) Min. 0 0 0 0 0 0 0 Typ. -- -- -- -- -- -- -- Max. 200 200 200 200 200 200 200 Unit ns ns ns ns ns ns ns 9/18 Semiconductor MSM7581 TIMING DIAGRAM CODER BCKP1 - 4 SYXP1 - 4 SIP1 - 4 BCKA1 - 4 SYXA1 - 4 SOA1 - 4 tSDX 0 tXS 1 MSB ,, ,, ,, 0 tXS 1 tSX 2 3 4 5 6 7 8 9 10 tDS tDH ,, ,, ,, ,, ,, ,, ,, , ,, ,, ,, LSB ,, ,, ,, , tSX tXD1 , 2 ,, ,, ,, , 3 4 ,, ,, ,, , 5 , ,, 6 ,, ,, 7 8 9 10 tXD2 MSB tXD3 LSB DECODER BCKA1 - 4 SYRA1 - 4 SIA1 - 4 BCKP1 - 4 SYRP1 - 4 SOP1 - 4 tSDR 0 tRS MSB ,, ,, 0 tRS 1 tSR 2 3 4 5 6 7 8 9 10 tDS tDH ,, ,, ,, LSB 4 5 6 7 8 9 10 tSR tRD1 MSB 1 ,, 2 ,, ,, ,, 3 ,, , tRD2 tRD3 LSB DET ("0000" detection) Output Timing BCKA1 - 4 SYRA1 - 4 Note) SIA1 - 4 "0000" "0000" DET1 - 4 tDD1 tDD2 Note: 4 bit data pattern except "0000" 10/18 Semiconductor PAD Processing Timing SYXA BCKA SIA 78.125ms Internal 12dBPAD processing Timing 121.09ms Internal MUTE processing Timing 78.125ms MSB LSB 78.125ms MSM7581 PAD10 to PAD40, PAD11 to PAD41 Timings SYXP PAD10, 11 ts Internal PAD Signal th ts=100ns or more th=100ns or more BCKP SOP MSB 0dB transmit data As mentioned above, PAD and MUTE processings are performed according to the rising edge of SYXA. Even if BLOCK is not 128 kHz, these processings are performed in the absolute time counted from the rising edge of SYXA. The PAD pin must be controlled so as to cover these processings. The PAD signal is input in the device at the rising edge of SYXP. Therefore, the PAD signal should be input at ts and th for the rise of SYXP. LSB PAD processing transmit data 0dB transmit data 11/18 Semiconductor MSM7581 THR Processing Timing Timing Block Diagrams, when CODER and DECODER output data, are shown in the following figures. The parallel to serial conversion of the output unit employs a load format and the load point is at the rising edge of a synchronous signal. Therefore, input THR signal with respect to SYXA for CODER with timing of satisfying ts and th conditions shown in the figure. For DECODER, THR signal should be input even of through-data is input. The input timing should satisfy the conditions shown in the following figures. CODER Through-data 8b SYXP SIP BCKP THR PCM side SYNC (SYXP) PCM Input (SIP) MSB LSB Parallel Latch timing=A Serial 8 ADPCM CODER S E L 4b Parallel Serial SYNCA SOA BCLKA Latch Internal Latch timing (A) Internal Input Data Through-data ADPCM side SYNC (SYXA) Through-data Output (SOA) BCKA THR ts th ts=100ns or more th=100ns or more MSB Note: That data-ship may occur when the rising edge (data load point) of SYXA and input of the internal latch timing overlap each other. 12/18 Semiconductor DECODER Through-data 8b SYNCA SIA BCLKA THR ADPCM side SYNC (SYXA) ADPCM Input (SIA) MSB LSB Parallel Latch timing=A Serial 8 ADPCM DECODER S E L 8b Parallel Serial MSM7581 SYNCP SOP BCLKP Latch Internal Latch timing (A) Internal Input Data Through-data This data is output here. PCM side SYNC (SYXP) Throgh-data output (SOP) BCLKP THR MSB Less than are BCLKP cycle from the rising edge of SYXA signal. 100ns or more 13/18 Semiconductor MSM7581 APPLICATION CIRCUIT DECODER 4 Side ADPCM Intput DECODER 3 Side ADPCM Intput CODER 4 Side ADPCM Output CODER 3 Side ADPCM Output VDD 8 kHz Synchronous Signal (Channel 4) VDD 8 kHz Synchronous Signal (Channel 3) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 PDN3 SYRA4 SYRA3 PDN4 BCKA3 SIA3 SOA3 SYXA4 BCKA4 SYXA3 PLCK3 SOA4 PLCK4 THR3 NC SIA4 DET3 NC NC NC NC THR4 VDD 76 77 78 DET4 NC NC NC RES3 51 NC RES4 SYRP4 SIP4 SOP4 BCKP4 NC SYXP4 PAD40 PAD41 NC 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VDD CODER 4 Side PCM Intput DECODER 4 Side PCM Output SYRP3 SIP3 SOP3 BCKP3 NC SYXP3 PAD30 PAD31 NC LAW 79 80 81 82 83 84 85 86 87 88 89 90 91 CODER 3 Side PCM Intput DECODER 3 Side PCM Output VDD PLCKEN VDD GND NC PAD11 PAD10 SYXP1 NC BCKP1 SOP1 SIP1 SYRP1 RES1 MSM7581 GND VDD NC PAD21 PAD20 SYXP2 NC BCKP2 SOP2 SIP2 SYRP2 RES2 GND VDD 92 93 94 95 VDD DECODER 1 Side PCM Output CODER 1 Side PCM Intput 96 97 98 99 100 DECODER 2 Side PCM Output CODER 2 Side PCM Intput SYRA1 SYRA2 SYXA1 BCKA1 BCKA2 SYXA2 PLCK1 PLCK2 PDN1 PDN2 SOA1 SOA2 THR1 THR2 24 DET1 DET2 SIA1 SIA2 NC NC 25 NC NC NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 NC 8 kHz Synchronous Signal (Channel 1) VDD VDD 8 kHz Synchronous Signal (Channel 2) Shift Clock (Channel 1 - 4) 64 kHz to 2048 kHz DECODER 2 Side ADPCM Intput VDD 0.1 mF GND + 10 mF CODER 1 Side ADPCM Output DECODER 1 Side ADPCM Intput CODER 2 Side ADPCM Output 14/18 Semiconductor MSM7581 NOTES ON USAGE (1) Through Mode (CODER Side) t0 BCLK PCM side SYNC (SYXP) PCM Input (SIP) Internal Latch Timing (A) ADPCM side SYNC (SYXA) Through-Data Output (SOA) ADPCMDATA0 ADPCMDATA1 ADPCMDATA2 PCMDATA1 PCMDATA2 PCMDATA3 1 2 3 4 5 6 7 8 t1 (B) ADPCM side SYNC (SYXA) Through-Data Output (SOA) ADPCMDATA0 *t1 is the falling edge of the 8th BCLK counted from t0. (A) When SYXA rises after t1, PCMDATA1 is output to ADPCMDATA1. (B) When SYXA rises before t1, PCMDATA1 is output to ADPCMDATA1. If SYXA rises near the t1 and jitter occurs, data slip may occur. Therefore SYXA should not rise in the range of 500ns from t1. The data slip means that data is deleted or the same data is output twice. ADPCMDATA1 (2) Through Mode (DECODER Side) t0 BCLK ADPCM side SYNC (SYRA) ADPCM Input (SIA) Internal Latch Timing (A) PCM side SYNC (SYRP) Through-Data Output (SOP) PCMDATA0 PCMDATA1 PCMDATA2 ADPCMDATA1 ADPCMDATA2 ADPCMDATA3 1 2 3 4 5 6 7 8 t1 (B) PCM side SYNC (SYRP) Through-Data Output (SOP) PCMDATA0 *t1 is the falling edge of the 8th BCLK counted from t0. (A) When SYRP rises after t1, ADPCMDATA1 is output to PCMDATA1. (B) When SYRP rises before t1, ADPCMDATA1 is output to PCMDATA1. If SYRP rises near the t1 and jitter occurs, data slip may occur. Therefore SYRP should not rise in the range of 500ns from t1. The data slip means that data is deleted or the same data is output twice. PCMDATA1 15/18 Semiconductor (3) PCMAEADPCM, ADPCMAEPCM during Transcode (a) CODER Timing Diagram t0 SYXA SYXP BCKP SIP Internal (1) Timing (2) Timing (3) 1 MSB MSM7581 2 3 4 5 6 7 8 LSB Tsip t4 104.2ms 119.8ms PCM Input Data A t1 t2 MSB * t4 is the falling edge of the 8th BCLK counted from the rising edge of SYXP. SOA LSB MSB LSB Tsoa t5 * t5 is the rising edge of SYXA. (b) DECODER Timing Diagram SYRA BCKA SIA Internal (6) SYRP Timing (4) Timing (5) 65.2ms t3 t2 PCM Output Data MSB LSB 1 MSB 2 3 4 LSB MSB ADPCM Input Data * t6 is the falling edge of the 4th BCLK counted from the rising edge of SYRA. Tsia Tsop t7 t6 * t7 is the rising edge of SYRP. B 119.8ms SOP (c) Internal Circuit Configuration SIP SYXP S / P (1) 8bit P / S SOA SYXA Latch To CODER (2) (5) From CODER (3) (4) Latch 8bit BCKP SYRP SOP P / S 8bit Latch PLL BCKA Latch (6) 8bit S / P SYRA SIA From DECODER To DECODER SYXA 16/18 Semiconductor MSM7581 In this device, internal operating signals are generated according to the ADPCM side SYNC (SYXA) signal. The timings are shouwn in the figures (a) and (b); The arithmetic operation of CODER is performed at "A" in the figure (a). The arithmetic operation of DECODER is performed at "B" in the figure (b). Therefore, when the conversion delay time Tsip of the CODER is less than t1, ADPCM is output at the timing of Tsoa. When Tsip is more than t1, ADPCM is output at the timing of Tsoa + 125ms. For DECODER, when Tsia Semiconductor MSM7581 PACKAGE DIMENSIONS (Unit : mm) TQFP100-P-1414-0.50-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.55 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 18/18 |
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